In a power transistor conventionally used for a chopper circuit and an inverter circuit, a breakdown phenomenon is caused by the so-called "dv/dt current".
That is, when, in a conventional chopper circuit, a transistor Tr.sub.B as shown in FIG. 1 repeats on-off operations, a transistor Tr.sub.A connected in parallel to a load L is subjected to a breakdown phenomenon caused by a "dv/dt current".
The breakdown phenomenon by the "dv/dt current" is caused in such a manner that, when an abrupt source voltage accompanying the on-operation of the transistor Tr.sub.B is applied between a collector and an emitter of the transistor Tr.sub.A, a high current to the transistor Tr.sub.A to increase an electrical loss, finally leading to breakdown of the transistor Tr.sub.A.
When, in the chopper circuit as shown in FIG. 1, the transistor Tr.sub.B is turned on, a voltage V.sub.CE between the collector and the emitter of the transistor Tr.sub.A and a source current I.sub.TD flowing to the transistor Tr.sub.A and a diode D.sub.A are changed as shown in FIG. 2.
Since, as shown in FIG. 2, a high source current I.sub.TD flows simultaneously with rising of the voltage V.sub.CE, the transistor Tr.sub.A generates significant heat in response to on-off operations of the transistor Tr.sub.B.
And, when the source voltage is further raised, the source current I.sub.TD is all the more increased, finally leading to breakdown of the transistor Tr.sub.A.
It is to be noted that the characteristics of the voltage V.sub.CE and the current I.sub.TD as shown in FIG. 2 are waveforms in a case where the base of the transistor Tr.sub.A is in an open state.
In a conventional Darlington-connected transistor structure, as shown in FIG. 3, a front stage transistor Tr.sub.1 and a rear stage transistor Tr.sub.2 are generally provided with resistances R.sub.EB1 and R.sub.EB2 between bases and emitters, respectively.
FIG. 4 is a plan view of the Darlington-connected transistor as shown in FIG. 3, and FIG. 5 is a cross-sectional view thereof taken along the line V--V in FIG. 4.
As shown in FIG. 5, a conventional Darlington-connected transistor structure comprises a first stage, or front stage transistor Tr.sub.1 and a second stage, or rear stage transistor Tr.sub.2, in which the front stage transistor Tr.sub.1 has an emitter layer (1), a base layer (6), a collector layer (5) and an emitter electrode (3), and the rear stage transistor Tr.sub.2 has an emitter layer (2) and a base layer (7) and a collector layer (5) respectively communicating with the base layer through a resistance and the collector layer of the front stage transistor Tr.sub.1.
Further, since the rear stage transistor Tr.sub.2 is connected with the front stage transistor Tr.sub.1 in a Darlington connection manner, the emitter electrode (3) of the front stage transistor Tr.sub.1 is electrically connected with a base electrode (4) of the rear stage transistor Tr.sub.2 as shown in FIG. 3.
Still further, for the purpose of adjusting the resistance R.sub.EB1 between the base and the emitter of the front stage transistor Tr.sub.1 as shown in FIG. 3 to an appropriate value, the resistance of the base layer (6) of the front stage transistor Tr.sub.1 has been increased by prolonging the emitter layer (1) of the front stage transistor Tr.sub.1 toward the rear stage transistor Tr.sub.2 as shown in FIG. 5.
However, in the Darlington-connected transistors of such structure, there is sometimes caused, in practice, increase of the so-called dv/dt current, which is a problem to be solved at this time. Thus, in a monolithic Darlington Structure, the first stage transistor needs to be substantially separated from the second stage transistor on the same chip. If such a separation is achieved by a typical mesa type structure, a groove must be formed between the transistors Tr1 and Tr2, as shown in FIGS. 24-25. Since the thickness of the N region in FIG. 25 is relatively larger in a high breakdown transistor, the width of such a groove cannot be neglected. In addition, due to such grooves, interconnection between the transistors Tr1 and Tr2 cannot be formed on the chip, which is very inconvenient.
For this reason, practical devices hardly ever adopt the structure shown in FIG. 24, but instead adopt the structure as shown in FIG. 26. In such a case, only the peripheral portion of a chip has a mesa structure. Such a structure is known in the prior art, as illustrated by the drawings in U.S. Pat. No. 4,136,355 to Mizukoshi.
In this type of structure, the base of the transistor Tr1 and the base of the transistor Tr2 are formed as a common region and hence the resistance between the bases of the transistors Tr1 and Tr2 becomes lower. As a result, the current amplifying factor of a transistor, hFE, cannot be made large, as described in the above mentioned patent. As a countermeasure for that, the dimension "l1" of the prior art patent is made longer so that resistance in both base regions can be made higher. Thus, it is clear that the prior art, illustrated by the Mizukoshi patent intends to provide a high resistance with small area, in an efficient manner.
However, the Mizukoshi patent discloses an obstruction part 131 which appears to provide a parasitic transistor as defined below. Where such a obstruction part is provided, the structure shown in the Mizukoshi patent is not sufficient to suppress operation of such a parasitic transistor. Instead, as described below, it is much more effective to separate the majority of connecting portion of the first and second stage transistors in their collector area (5), as shown in FIGS. 10, 13 and 14 of the present application.
Thus, the Mizukoshi structure offers no advantages for a monolithic transistor of a type having a planar structure. Indeed, the structure of the prior art is basically inferior to a planar device as described herein, from the view point of adverse influence by a parasitic transistor formed therein, which is eliminated by the present invention.